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1 direct r ambus rimm ? with 128/144m bi t rdrams preliminary this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.0/ dec. 99 overview the rambus ? rimm tm module is a general purpose high- performance memory subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. the rambus rimm module consist of 128mb/144mb direct rambus dram devices. these are extremely high- speed cmos drams organized as 8m words by 16 or 18 bits. the use of rambus signaling level (rsl) technology permits 600mhz ,711mhz or 800mhz transfer rates while using conventional system and board design technologies. direct rdram devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per 16 bytes). the rdram architecture enables the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. the separate control and data buses with independent row and column control yield over 95% bus efficiency. the direct rdram's 16-banks architecture supports up to four simultaneous transactions per device. features w high speed 800,711 and 600 mhz rdram storage w 184 edge connector pads with 1 mm pad spacing w maximum module pcb size: 133.5mm x 31.75mm x 1.37mm(5.21 ? x 1.25 ? x 0.05 ? ) w each rdram has 32 banks, for a total of 512, 384, 256, 192 or 128 banks on each 256mb, 192mb, 128mb, 96mb, or 64mb module respectively w gold plated edge connector pad contacts w serial presence detect(spd) support w operates from a 2.5 volt supply ( ?? 5%) w low power and powerdown self refresh modes w separate row and column buses for higher efficiency key timing parameters/part numbers the following table lists the frequency and latency bins available from rimm modules. an optional -lp designator is used to indicate low power modules. form factor the rambus rimm modules are offered in a 184-pad 1mm edge connector pad pitch from factor suitable for either 184 or 168 contact rimm connectors. the rimm module is suitable for desktop and other system applications. figure 1 shows an eight device rambus rimm module without heat spreader. table 1: rimm module frequency and latency organization i/o freq . mhz t rac (row access time) ns x16 600 53 x16 711 45 x16 800 40 x18 600 53 x18 711 45 x18 800 45 x18 800 40 x16 800 45
2 rev.1.0 dec.99 rimm with 128/144mb rdram pin pin name pin pin name pin pin name pin pin name a1 gnd b1 gnd a47 nc b47 nc a2 ldqa8 b2 ldqa7 a48 nc b48 nc a3 gnd b3 gnd a49 nc b49 nc a4 ldqa6 b4 ldqa5 a50 nc b50 nc a5 gnd b5 gnd a51 vref b51 vref a6 ldqa4 b6 ldqa3 a52 gnd b52 gnd a7 gnd b7 gnd a53 scl b53 sa0 a8 ldqa2 b8 ldqa1 a54 vdd b54 vdd a9 gnd b9 gnd a55 sda b55 sa1 a10 ldqa0 b10 lcfm a56 svdd b56 svdd a11 gnd b11 gnd a57 swp b57 sa2 a12 lctmn b12 lcfmn a58 vdd b58 vdd a13 gnd b13 gnd a59 rsck b59 rcmd a14 lctm b14 nc a60 gnd b60 gnd a15 gnd b15 gnd a61 rdqb7 b61 rdqb8 a16 nc b16 lrow2 a62 gnd b62 gnd a17 gnd b17 gnd a63 rdqb5 b63 rdqb6 a18 lrow1 b18 lrow0 a64 gnd b64 gnd a19 gnd b19 gnd a65 rdqb3 b65 rdqb4 a20 lcol4 b20 lcol3 a66 gnd b66 gnd a21 gnd b21 gnd a67 rdqb1 b67 rdqb2 a22 lcol2 b22 lcol1 a68 gnd b68 gnd a23 gnd b23 gnd a69 rcol0 b69 rdqb0 a24 lcol0 b24 ldqb0 a70 gnd b70 gnd a25 gnd b25 gnd a71 rcol2 b71 rcol1 a26 ldqb1 b26 ldqb2 a72 gnd b72 gnd a27 gnd b27 gnd a73 rcol4 b73 rcol3 a28 ldqb3 b28 ldqb4 a74 gnd b74 gnd a29 gnd b29 gnd a75 rrow1 b75 rrow0 a30 ldqb5 b30 ldqb6 a76 gnd b76 gnd a31 gnd b31 gnd a77 nc b77 rrow2 a32 ldqb7 b32 ldqb8 a78 gnd b78 gnd a33 gnd b33 gnd a79 rctm b79 nc a34 lsck b34 lcmd a80 gnd b80 gnd a35 vcmos b35 vcmos a81 rctmn b81 rcfmn a36 sout b36 sin a82 gnd b82 gnd a37 vcmos b37 vcmos a83 rdqa0 b83 rcfm a38 nc b38 nc a84 gnd b84 gnd a39 gnd b39 gnd a85 rdqa2 b85 rdqa1 a40 nc b40 nc a86 gnd b86 gnd a41 vdd b41 vdd a87 rdqa4 b87 rdqa3 a42 vdd b42 vdd a88 gnd b88 gnd a43 nc b43 nc a89 rdqa6 b89 rdqa5 a44 nc b44 nc a90 gnd b90 gnd a45 nc b45 nc a91 rdqa8 b91 rdqa7 a46 nc b46 nc a92 gnd b92 gnd table 2: module pad number and signal names
rev.1.0 dec.99 3 rimm with 128/144mb rdram table 3: module connector pad description module connector pads i/o signal type description a1, a3, a5, a7, a9, a11, a13, a15, a17, a19, a21, a23, a25, a27, a29, a31, a33, a39, a52, a60, a62, a64, a66, a68, a70, a72, a74, a76, a78, a80, a82, a84, a86, a88, a90, a92, b1, b3, b5, b7, b9, b11, b13, b15, b17, b19, b21, b23, b25, b27, b29, b31, b33, b39, b52, b60, b62, b64, b66, b68, b70, b72, b74, b76, b78, b80, b82, b84, b86, b88, b90, b92 gnd ground reference for rdram core and interface. 72 pcb connector pads. b10 i lcfm rsl clock from master. interface clock used for receiv - ing rsl signals from the channel. positive polarity. b12 i lcfmn rsl clock from master. interface clock used for receiv - ing rsl signals from the channel. negative polarity. b81 i rcfmn rsl clock from master. interface clock used for receiv - ing rsl signals from the channel. negative polar- ity . b34 i lcmd v cmos serial command used to read from and write to the control registers. also used for power management. a20, b20, a22, b22, a24 i lcol4.. lcol0 rsl column bus. 5-bit bus containing control and add- ress information for column accesses. a14 i lctm rsl clock to master. interface clock used for transmit- ting rsl signals to the channel. positive polarity. a12 i lctmn rsl clock to master. interface clock used for transmit- ting rsl signals to the channel. negative polarity. a2, b2, a4, b4, a6, b6, a8, b8, a10 i/o ldqa8.. ldqa0 rsl data bus a. a 9-bit bus carrying a byte of read or write data between the channel and the rdram. ldqa8 is non-functional on x16 rdram devices. b32, a32, b30, a30, b28, a28, b26, a26, b24 i/o ldqb8.. ldqb0 rsl data bus b. a 9-bit bus carrying a byte of read or write data between the channel and the rdram. ldqb8 is non-functional on x16 rdram devices. b16, a18, b18 i lrow2.. lrow0 rsl row bus. 3-bit bus containing control and address information for row accesses. a34 i lsck v cmos serial clock input. clock source used to read from and write to the rdram control registers. a16, b14, a38, b38, a40, b40, a77, b79 nc these pads are not connected. these 8 connector pads are reserved for future use. a43, b43, a44, b44, a45, b45, a46, b46, a47, b47, a48, b48, a49, b49, a50, b50 nc these pads are not connected. these 16connector pads art reserved for future use. the 168 contact rimm connector does not connect to these pcb pads. b83 i rcfm rsl clock from master. interface clock used for receiv - ing rsl signals from the channel. positive polarity.
4 rev.1.0 dec.99 rimm with 128/144mb rdram module connector pads i/o signal type description b59 rcmd serial command input used to read from and write to the control registers. also used for power management. i v cmos a73, b73, a71, b71, a69 i rcol4.. rcol0 rsl column bus. 5-bit bus containing control and address information for column accesses. a41, a42, a54, a58, b41, b42, b54, b58 i vdd supply voltage for the rdram core and interface logic. a79 i rctm rsl clock to master. interface clock used for transmit- ting rsl signals to the channel. positive polarity. a81 i rctmn rsl clock to master. interface clock used for transmit- ting rsl signals to the channel. negative polarity. a91, b91, a89, b89, a87, b87, a85, b85, a83 i/o rdqa8.. rdqa0 rsl data bus a. a 9-bit bus carrying a byte of read or write data between the channel and the rdram. rdqa8 is non-functional on x16 rdram devices. b61, a61, b63, a63, b65, a65, b67, a67, b69 i/o rdqb8.. rdqb0 rsl data bus b. a 9-bit bus carrying a byte of read or write data between the channel and the rdram. rdqb8 is non-functional on x16 rdram devices. b77, a75, b75 i rrow2.. rrow0 rsl row bus. 3-bit bus containing control and address information for row accesses. a59 i rsck v cmos serial clock input. clock source used to read from and write to the rdram control registers. b53 i sa0 sv dd serial presence detect address 0. b55 i sa1 sv dd serial presence detect address 1. b57 i sa2 sv dd serial presence detect address 2. a53 i scl sv dd serial presence detect clock. a55 i/o sda sv dd serial presence detect data (open collector i/o) b36 i/o sin v cmos serial i/o for reading from and writing to the control registers. attaches to sio0 of the first rdram on the module. a36 i/o sout v cmos serial i/o for reading from and writing to the control registers. attaches to sio1 of the last rdram on the module. a56, b56 sv dd spd voltage. used for signals scl, sda, swe, sa0, sa1 and sa2. a57 i swp sv dd serial presence detect write protect (active high). when low, the spd can be written as well as read. a35, b35, a37, b37 v cmos cmos i/o voltage. used for signals cmd, sck, sin, sout. a51, b51 vref logic threshold reference voltage for rsl signals.
rev.1.0 dec.99 5 rimm with 128/144mb rdram dqa8 dqa7 dqa6 dqa5 dqa4 dqa3 dqa2 dqa1 dqa0 cfm cfmn ctm ctmn row2 row1 row0 col4 col3 col2 col1 col0 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 dqb6 dqb7 dqb8 sio0 sio1 sck cmd vref direct rdram (128/144mb) u1 dqa8 dqa7 dqa6 dqa5 dqa4 dqa3 dqa2 dqa1 dqa0 cfm cfmn ctm ctmn row2 row1 row0 col4 col3 col2 col1 col0 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 dqb6 dqb7 dqb8 sio0 sio1 sck cmd vref direct rdram (128/144mb) u2 ldqa8 ldqa7 ldqa6 ldqa5 ldqa4 ldqa3 ldqa2 ldqa1 ldqa0 lcfm lcfmn lctm lctmn lrow2 lrow1 lrow0 lcol4 lcol3 lcol2 lcol1 lcol0 ldqb0 ldqb1 ldqb2 ldqb3 ldqb4 ldqb5 ldqb6 ldqb7 ldqb8 dqa8 dqa7 dqa6 dqa5 dqa4 dqa3 dqa2 dqa1 dqa0 cfm cfmn ctm ctmn row2 row1 row0 col4 col3 col2 col1 col0 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 dqb6 dqb7 dqb8 sio0 sio1 sck cmd vref direct rdram (128/144mb) u3 rdqa8 rdqa7 rdqa6 rdqa5 rdqa4 rdqa3 rdqa2 rdqa1 rdqa0 rcfm rcfmn rctm rctmn rrow2 rrow1 rrow0 rcol4 rcol3 rcol2 rcol1 rcol0 rdqb0 rdqb1 rdqb2 rdqb3 rdqb4 rdqb5 rdqb6 rdqb7 rdqb8 sin lsck lcmd v ref sout rlsck rcmd sv dd scl swp sa0 sa1 sa2 v cc scl sda wp a0a1a2 sda serial presence detect 0.1 t sv dd gnd 2 per rdram 0.1 t vdd gnd 1 per 2 rdrams plus one near connector 0.1 t v ref gnd 1 per 2 rdrams 0.1 t v cmos gnd note 1: rambus channel signals form a loop through the rimm module, with the exception of the sio chain. note 2: see serial presence detection specification for information on the spd device and its contents figure 2: rimm module functional diagram dqa8 dqa7 dqa6 dqa5 dqa4 dqa3 dqa2 dqa1 dqa0 cfm cfmn ctm ctmn row2 row1 row0 col4 col3 col2 col1 col0 dqb0 dqb1 dqb2 dqb3 dqb4 dqb5 dqb6 dqb7 dqb8 sio0 sio1 sck cmd vref direct rdram (128/144mb) un module capacity n 256 mb 16 192 mb 12 128 mb 8 96 mb 6 64 mb 4
6 rev.1.0 dec.99 rimm with 128/144mb rdram absolute maximum ratings dc recommended electrical conditions a. the tale below shows the number of 128mb or 144mb rdram devices contained in a rimm module of listed memory storage capacity parameter min signal max unit voltage applied to any rsl or cmos pin with respect to gnd v i,abs v - 0.3 v dd + 0.3 voltage on vdd with respect to gnd v dd,abs v - 0.5 v dd + 1.0 storage temperature t store o c - 50 100 parameter and conditions signal max unit supply voltage v dd v 2.50 + 0.13 cmos i/o power supply at pad for 2.5v controllers: cmos i/o power supply at pad for 1.8v controllers: v cmos v v 2.5 + 0.25 1.8 + 0.2 min 2.50 - 0.13 2.5 - 0.13 1.8 - 0.1 reference voltage v ref v 1.4 + 0.2 1.4 - 0.2 rsl input low voltage v il v v ref - 0.2 v ref - 0.5 rsl input high voltage v ih v v ref + 0.5 v ref + 0.2 cmos input low voltage v il,cmos v 0.5 v cmos - 0.25 - 0.3 cmos input high voltage v ih,cmos v v cmos + 0.3 0.5 v cmos + 0.25 cmos output low voltage @ i ol,cmos = 1 ma v ol,cmos v 0.3 cmos output high voltage @ i oh,cmos = -0.25 ma v oh,cmos v v cmos - 0.3 v ref current @ v ref,max i ref ? 10 x no. rdrams a -10 x no. rdrams a cmos input leakage current @ (0 v cmos v dd ) i sck,cmd ? 10 x no. rdrams a -10 x no. rdrams a cmos input leakage current @ (0 v cmos v dd ) i sin,sout ? 10.0 -10.0 rimm module capacity: 256 mb 192 mb 128 mb 96 mb 64 mb number of 128mb or 144mb rdram devices: 16 12 8 6 4
rev.1.0 dec.99 7 rimm with 128/144mb rdram rimm module current profile a. specifications in this table are maximum guidelines. actual power will depend on individual rdram component specifications, memory controller and usage patterns. please refer to specific rimm module vendor data sheets for additional information. max current computed for x18 144mb rdrams . x16 128mb rdrams use 8ma less current per rdram in read. b. i/o current is a function of the % of 1 ? s, to add i/o power for 50% 1 ? s for a x16 need to add 257ma or 290ma for x18ecc module for the following : v dd = 2.5v, v term = 1.8v, v ref = 1.4v and v dil = v ref - 0.5v. rimm module capacity: no. of 128/144mb rdrams : i dd unit one rdram in read b , balance in nap mode 64/72 mb 4 96/108 mb 6 128/144 mb 8 192/216 mb 12 256/288 mb 16 rimm module power conditions a max max max max max ma i dd1 one rdram in read b , balance in standby mode ma i dd2 one rdram in read b , balance in active mode ma i dd3 one rdram in write, balance in nap mode ma i dd4 one rdram in read, balance in standby mode ma i dd5 one rdram in read, balance in active mode ma i dd6 freq . 800 711 600 800 711 600 800 711 600 800 711 600 800 711 600 800 711 600 690/658 633/605 556/532 2302/2354 2142/2199 1928/2005 3506/3560 3222/3318 2889/3006 794/766 765/705 668/625 2405/2462 2273/2298 2040/2098 3609/3668 3353/3418 3002/3100 675/641 618/589 541/516 1857/1885 1725/1757 1547/1596 2740/2769 2517/2578 2253/2331 778/750 750/688 654/609 1960/1993 1856/1857 1660/1690 2843/2878 2648/2678 2365/2424 660/625 603/572 527/500 1412/1416 1307/1316 1167/1188 1974/1979 1811/1838 1616/1655 763/733 735/672 639/594 1515/1524 1439/1415 1280/1281 2077/2087 1943/1938 1729/1748 652/616 596/564 520/492 1189/1181 1099/1095 977/983 1591/1583 1459/1468 1297/1317 756/724 728/663 632/586 1293/1290 1230/1195 1090/1077 1694/1692 1590/1568 1410/1410 645/608 589/556 512/484 967/947 890/874 787/779 1208/1188 1106/1098 979/979 748/716 720/655 625/578 1070/1055 1022/974 900/872 1311/1296 1238/1198 1092/1073
8 rev.1.0 dec.99 rimm with 128/144mb rdram adjusted ? t pd specification parameter and conditions symbol unit propagation delay variation of rsl signals with respect to t pd for 4,6 and 8 device modules ns propagation delay variation of rsl signals with respect to t pd for 12 device modules ? t pd ps asolute min/max 40 -30 -40 adjusted min/max +/-[17+(18* n* ? z0)] a +/-[20+(18* n* ? z0)] a 30 propagation delay variation of rsl signals with respect to t pd for 16 device modules ps 50 -50 +/-[24+(18* n* ? z0)] a a. where : n =number of rdram devices installed on the rimm module ? z0 = delta z0% = (max z0 - min z0)/(min z0) (max z0 and min z0 are obtained from the loaded (high impedance) impedance coupons of all rsl layers on the modules) ac electrical specifications parameter and condition symbol unit module impedance z ? average clock delay form finger to finger of all rsl clock nets (ctmn, cfm, and cfmn) t pd ns propagation delay variation of rsl signals with respect to t pd b ,c for 4, 6, 8, and 12 device modules ? t pd ps max 30.8 21 typ 28 min 25.2 - -21 see table a propagation delay variation of sck and cmd signals with respect to an average clock delay b ? t pd-cmos ps 100 -100 attenuation limit v /v in % see table a forward crosstalk coefficient (300ps input rise time 20%-80%) v xf /v in % see table a backward crosstalk coefficient (300ps input rise time 20%-80%) v xb /v in % see table a a. table below lists parameters and specifications for different storage capacity rimm modules that use 128mb or 144mb rdram devices. b. t pd or average clock delay is defined as the average delay from finger to finger of all rsl clock nets (ctm, ctmn, cfm, and cfmn) c. if the rimm module meets the following specification , then it is compliant to the specification. if the rimm module does not meet these specification. then the specification can be adjusted by the ? adjusted ? t pd specification ? table propagation delay variation of rsl signals with respect to t pd b ,c for 16 device modules ps 24 -24
9 direct r ambus rimm ? with 128/144m bi t rdrams preliminary rev. 1.0/dec.99 ac electrical specifications for rimm modules rimm module capacity: no. of 128/144mb rdrams : symbol unit propagation delay, all rsl signals -800,-711 64/72 mb 4 96/108 mb 6 128/144 mb 8 2.06 192/216 mb 12 256/288 mb 16 parameter and condition for -800 & -600 rimm module max max max max max 1.76 1.50 1.4 1.25 ns propagation delay, all rsl signals -600 2.10 1.76 1.60 1.40 1.25 ns t pd attenuation limit -800,-711 25 20 16 14 12 % attenuation limit -600 21 18 10 9 8 % v /v in forward crosstalk coefficient (300ps input rise time @ 20%-80%) -800,-711 8 6 4 3 2 % v xf /v in forward crosstalk coefficient (300ps input rise time @ 20%-80%) -600 8 6 4 3 2 % backward crosstalk coefficient (300ps input rise time @ 20%-80%) -800,-711 2.5 2.3 2.0 1.8 1.5 % v xb /v in backward crosstalk coefficient (300ps input rise time @ 20%-80%) -600 2.5 2.3 2.0 1.8 1.5 % dc resistance limit -800,-711 1.2 1.1 0.8 0.7 0.6 ? dc resistance limit -600 r dc 1.2 1.1 0.8 0.7 0.6 ?
10 rev.1.0 dec.99 rimm with 128/144mb rdram the following defines the rimm module dimensions. all units are in millimeters. the height of the module is 31.75mm. physical dimensions note 1.tolerances on all dimensions ?? 0.127mm unless otherwise specified. 2.thickness(* mark) includes plating and/or metallization . 133.35 ?? 0.15 3.0 4.0 ?? 0.15 r 2.0 17.78 5.675 45.0 55.175 ?? 0.08 27.5 4.5 11.5 31.75 1.27 ?? 0.1 a1 a92 detail a detail b 3.0 ?? 0.1 r 1.0 2.0 ?? 0.1 1.0 0.8 ?? 0.1 2.99 ?? 0.05 0.15 ?? 0.1 detail a detail b b1 b92 top area - n components figure 3: rimm module pcb physical description max. 7.37 including heat spreader the maximum rimm module weight is 75gm(2.625oz) with a center of mass 35mm (1.378 in.) upwards from bottom edge. module weight
1 serial presence detect this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.0/ dec. 99 serial presence detect contents the following table lists the contents of the serial presence detect device. byte (dec) description option entry symbol value (hex) 0 spd revision level 1 total number of bytes in the spd 2 device type 3 module type 4 row address bits, column address bits 5 bank address bits and byte 6 refresh bank bits 7 t ref - refresh interval 8 protocol version 9 miscellaneous device configuration field 10 t rp -r,min 11 t ras -r,min 12 t rcd -r,min 13 t rr -r,min 256 08 drdram 01 rimm 01 9,6 96 16 d (4 bank bits) 84 5 05 32 t ref 20 2 02 - lp 1 t sck t dqs ,min - no -lp - lp s28ieco no -lp s28ieco 01 - 05 -40-800 08 -45-800 -45-711 -53-600 8 cycles t rp -r,min 08 8 cycles t rp -r,min 08 8 cycles t rp -r,min 08 8 cycles t rp -r,min 14 20 cycles t ras -r,min 14 20 cycles t ras -r,min 14 20 cycles t ras -r,min 14 20 cycles t ras -r,min 08 8 cycles t rcd -r,min 0 a 10 cycles t rcd -r,min 08 8 cycles t rcd -r,min 08 8 cycles t rcd -r,min 08 8 cycles t rr -r,min 08 8 cycles t rr -r,min 08 8 cycles t rr -r,min 2 02 -40-800 -45-800 -45-711 -53-600 -40-800 -45-800 -45-711 -53-600 -40-800 -45-800 -45-711 -53-600 08 8 cycles t rr -r,min 32 d (5 bank bits) c5 72 m 128/144 m 9,6 04 72 m 128/144 m
2 rev.1.0 dec.99 serial presence detect 14 t pp -r,min 8 cycles 8 cycles 8 cycles t pp -r,min t pp -r,min t pp -r,min 08 08 08 15 min t cycle for range a 13 2.50 ns t cycle t cycle t cycle t cycle 13 15 1 a 2.50 ns 2.80 ns 3.33 ns 16 max t cycle for range a 1 e 3.83 ns t cycle t cycle t cycle t cycle 1 e 1 e 1 e 3.83 ns 3.83 ns 3.83 ns 17 t cdly range for range a 59 5 - 9 t cycle 59 5 - 9 t cycle 59 5 - 9 t cycle 59 5 - 9 t cycle 18 t cls and t cas range for range a aa 00 19 min t cycle for range b reserved 0 00 20 max t cycle for range b reserved 0 00 21 t cdly range for range b reserved 0 00 22 t cls and t cas range for range b reserved 0 00 23 min t cycle for range c reserved 0 00 24 max t cycle for range c reserved 0 00 25 t cdly range for range c reserved 0 -40-800 -45-800 -45-711 -53-600 8 cycles t pp -r,min 08 -40-800 -45-800 -45-711 -53-600 -40-800 -45-800 -45-711 -53-600 -40-800 -45-800 -45-711 -53-600 2 t cycle for t cycle & t cycle t cycle 00 26 t cls and t cas range for range c reserved 0 00 27 min t cycle for range d reserved 0 00 28 max t cycle for range d reserved 0 00 29 t cdly range for range d reserved 0 00 30 t cls and t cas range for range d reserved 0 04 31 t pdnxa ,max t pdnxa ,max 4 ? 8 d 32 t pdnxb ,max t pdnxb ,max 9000 cylces 32 33 t napxa ,max t napxa ,max 50 ns 28 34 t napxb ,max t napxb ,max 40 ns 11 35 f imin [11:8], f imax [11:8] 261 mhz, 400mhz 11 261 mhz, 357mhz -800 -711 11 261 mhz, 300mhz -600 f imin f imax byte (dec) description option entry symbol value (hex)
rev.1.0 dec.99 3 serial presence detect 05 36 f imin [7:0] 261 mhz 05 261 mhz -800 -600 f imin 90 37 f imax [7:0] 400 mhz 2 c 300 mhz -800 -600 f imax 00 38 reserved 64 39 max. time between current control t cctrl ,max 100 ms 64 40 max. time between temp. calibration t temp ,max 100 ms 96 41 max. time between temp. calibration enable and command t tcen ,min 150 t cycle 40 42 maximum ras to precharge time t ras -r, max 64 ? 0 a 43 maximum time that a device can stay in nap mode t nlimit , max 10 ? 66 44 actrefpt, pchrefpt t cycle 6, 6 t cycle 55 45 cpchrefpt_dc, rdrefpt_dc t cycle 5, 5 t cycle 5 d 46 retrefpt_dc, wrrefpt_dc t cycle 5, 13 t cycle 00 47~49 reserved 01 50 f ras [11:8] 01 01 01 -800 -711 f ras 90 51 f ras [7:0] 90 2 c 2 c -800 -600 f ras 24 52 pmax, hi, pmax, lo, tj (assumes active-write current is max, tj = 100) 0,0,(100-64) 24 -800 -600 ? 0,0,(100-64) a4 53 heat spreader, tplate (assumes heat spreader present, tplate = 100) 1,(100-64) a4 -800 -711 ? 1,(100-64) 05 261 mhz -711 65 357 mhz -711 01 01 -600 65 65 -711 -711 24 0,0,(100-64) a4 -600 1,(100-64) byte (dec) description option entry symbol value (hex) - 54 pstby,hi tbd - ma tbd - 55 pacti,hi tbd - tbd - 56 pactrw,hi tbd - tbd 57 pstby,lo 58 pacti,lo 59 pactrw,lo ma ma ma ma ma - tbd - reserved 60 pnap 61 presa ma -
4 rev.1.0 dec.99 serial presence detect - reserved - tbd 62 presb 63 checksum for locations 0 - 62 - 64 - 71 manufacturer id code - tbd - 72 module manufacturing location - tbd - 73 - 90 module part number - tbd - 91 - 92 module revision code - tbd - 93 module manufacturing year - tbd - 94 module manufacturing week - tbd - 95 - 98 module serial number - tbd 10 99 number of devices on module 16 10 100 number of devices on module bit 16 12 18 x16 x18 101 device enables all 4 - - 4 d 6 d 8 d 12 d 16 d 0 c 12 08 8 06 6 04 ea 4 4 d 6 d 8 d 12 d 16 d ff ff ff 3 f 0 f all 6 all 8 all 16 all 16 bit 102 device enables - 4 d 6 d 8 d 12 d 16 d ff 0 f 00 00 00 - - all12 all 16 bit byte (dec) description option entry symbol value (hex) 103~104 - bit 00 10 105 module vdd , module voltage interface level 2.5 v, 1.8v v dd , v term 106 module v dd tolerance 52 5% dc, 2% ac 107-113 reserved device enables 20 115 cdly0/1 for tcdly = 4 t cycle 30 116 cdly0/1 for tcdly = 5 t cycle 2/0 31 117 cdly0/1 for tcdly = 6 t cycle 3/0 32 118 cdly0/1 for tcdly = 7 t cycle 3/1 42 119 cdly0/1 for tcdly = 8 t cycle 3/2 52 120 cdly0/1 for tcdly = 9 t cycle 4/2 5/2 00 114 cdly0/1 for tcdly = 3 t cycle -
rev.1.0 dec.99 5 serial presence detect eeprom component ac and dc characteristics symbol parameter test condition min max unit sv dd power supply 2.2 3.6 v i svdd active power supply current f scl = 100 khz 5.0 ma i svdd1 standby current v in = gnd or sv dd 100 ? i sli input leakage current v in = gnd or sv dd 10 ? i slo output leakage current v out = gnd or sv dd 10 ? v sil input low voltage -0.3 sv dd x 0.3 v v sih input high voltage sv dd x 0.7 sv dd + 0.3 v v sol output low voltage i sol = 3.0 ma 0.4 v 00 121 cdly0/1 for tcdly = 10 t cycle 00 122 cdly0/1 for tcdly = 11 t cycle - 00 123 cdly0/1 for tcdly = 12 t cycle 00 124 cdly0/1 for tcdly = 13 t cycle 00 125 cdly0/1 for tcdly = 14 t cycle 00 126 cdly0/1 for tcdly = 15 t cycle - - - - - undefined 127 checksum for bytes 99 - 126 tbd tbd undefined 128+ open for customer use - - byte (dec) description option entry symbol value (hex)
6 rev.1.0 dec.99 serial presence detect spd timing diagram eeprom component ac timing parameters symbol parameter and conditions min max unit f scl scl frequency 100 khz t 1 noise suppression time constant for scl, sda 100 ns t saa scl low to sda data out valid 0.3 0.7 ? t sbuf time bus must be free before a new transmission can start 6.7 ? t shd :sta start condition hold time 4.5 ? t slow clock low time 6.7 ? t shigh clock high time 4.5 ? t ssu :sta start condition setup time 6.7 ? t shd :dat data in hold time 0 ? t ssu :dat data in setup time 500 ns t sr sda and scl rise time 1 ? t sf sda and scl fall time 300 ns t ssu :sto stop condition setup time 6.7 ? t sdh data out hold time 300 ns t swr eeprom write cycle time 15 ms
direct rdram module ordering information direct rdram module ordering information memory depth module revision none : original m : first n : second die generation x xx xx data width 32 : 32 m , 48 : 48m 64 : 64m , 96 : 96m 128 : 128m , 256 : 256m 16 : x16 (non ecc) 18 : x18 (ecc) xx x 53 : 53 ns 50 : 50ns 45 : 45ns 40 : 40ns speed 6 : 600 mhz 7 : 711mhz 8 : 800mhz i/o frequency * x * speed = t rac : row access time x power supply and interface none : 2.5v w : 1.8v hyundai module hym ichon none : 1st gen . a : 2nd gen . b : 3rd gen . c : 4th gen . cheongju h : 1st gen . h a : 2nd gen . h b : 3rd gen . h c : 4th gen . xx component group r1 : 128mb/144mb d-rdram r2 : 256mb/288mb d-rdram r5 : 512mb/576mb d-rdram x module type none : 184pin rimm m : so rimm

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